1. Field of the Invention
The present invention generally relates to a horizontal synchronizing signal-generating circuit and, more particularly, to a horizontal synchronizing signal-generating circuit for separating and generating horizontal synchronizing signals from composite synchronizing signals for television or video tape recorder (VTR) images and the like.
2. Description of the Related Art
Composite synchronizing signals generally include horizontal synchronizing ("sync") signals and vertical synchronizing signals. Each of these synchronizing signals is a signal for indicating a timing for television (hereafter "TV") systems to scan pictures on cathode ray tubes (CRTs).
Specifically, the baseband signal for television is a composite of the visual information signals and synchronization signals. The visual information is transmitted as three signal components including a Y-luminance component, an I-chrominance component, and a Q-chrominance component. The I-chrominance and Q-chrominance components together convey information on the hue or tint and on the amount of saturation of the coloring which is present (assuming a color receiver/monitor). Monochrome receivers only require the Y-component.
The synchronization signal consists of narrow pulses at the end of each line scan for horizontal synchronization, and a sequence of narrower and wider pulses at the end of each field scan for vertical synchronization. Additional synchronization for the color information demodulation in the receiver is superimposed on the horizontal pulses as mentioned below.
Horizontal synchronizing signal-generating circuits are circuits for separating horizontal synchronizing signals from such composite synchronizing signals.
Referring to FIG. 6 which illustrates waveforms of composite synchronizing signals, the composite synchronizing signals include the above-mentioned horizontal synchronizing signals H and vertical synchronizing signals V. These horizontal and vertical synchronizing signals are for initializing horizontal (e.g., side-to-side) scanning with a timing provided by the horizontal synchronizing signals H, and for initializing vertical (e.g., up-and-down) scanning with a timing provided by the vertical synchronizing signals V.
The composite synchronizing signals (e.g., H and V) are extracted from composite picture signals received and decoded by TV tuners. Occasionally, disturbances occur depending on the state of the radio waves at the time of reception, including superimposition of noise, loss of some synchronizing signals, etc. This is an important consideration when the configuration and the function of a horizontal synchronizing signal-generating circuit are designed.
Besides horizontal and vertical synchronizing signals, composite synchronizing signals also include additional signals referred to as "serrated pulses P" and "equalizing pulses Q" near (adjacent) the vertical synchronizing signals V. Serrated pulses P are for indicating the horizontal pulses, whereas equalizing pulses Q are for recognizing the vertical synchronous period (e.g., they are input only around (adjacent) the vertical synchronous period). The equalizing and serrated pulses serve to stabilize the horizontal synchronizing inputs and may be set to a predetermined (e.g., two times) value of the frequency of the horizontal synchronizing inputs. Thus, these pulses serve to provide continuity to the horizontal inputs during a blanking period.
Additionally, there are two patterns of composite synchronizing signals referred to as an "odd field" and an "even field" due to a phase difference between the horizontal synchronizing signals H and the vertical synchronizing signals V. For purposes of this application, an "odd field" pattern is the pattern represented by the odd-numbered lines scanned, whereas an "even field" pattern is the pattern represented by the even-numbered lines scanned. As mentioned above, horizontal synchronizing signal-generating circuits have the function of extracting horizontal synchronizing signals from composite synchronizing signals.
Hereinafter, for convenience and brevity, the horizontal synchronizing signals, inputted as components of composite synchronizing signals, and the extracted and outputted horizontal synchronizing signals, are referred to simply as "horizontal synchronizing inputs" and "horizontal synchronizing outputs", respectively. Further, the periods during which vertical synchronizing signals are inputted are referred to simply as "vertical synchronization periods". The Q pulses are output only around (e.g., adjacent) the vertical synchronizing period.
Referring to FIG. 7, a conventional horizontal synchronizing signal-generating circuit includes a trailing-edge detecting circuit 1 which detects a transition of composite synchronizing signals from a high-level (e.g., a "1") to a low-level (e.g., a "0"), thereby to output a pulse-like, edge-detecting signal E. A counter 6 counts up the pulse number of a count clock CK and initializes the count number to zero by a counter-clearing signal CC.
A count number decoder 7 monitors the count of the counter 6, and sets an H-output reset signal A, a mask-canceling signal B and a self-generated output signal C, respectively, when the count number N has reached first through third settings ("1").
Briefly, the first setting is a value such that matching occurs 5 .mu.s after initialization of the counter 6, since the pulse width of the horizontal synchronizing inputs of the composite synchronizing signal SY is on the order of 5 .mu.s, as mentioned below.
The second setting is for preventing false inputting of the composite synchronizing signal SY due to noise, etc., and as mentioned below is usually set to approximately 93-95% of the cycle of the horizontal synchronizing inputs (e.g., an "approximate" horizontal synchronization signal).
The third setting is a value indicating the cycle of the horizontal synchronizing inputs (e.g., approximately 63.5 .mu.s or 64 .mu.s as shown in FIGS. 8(A) and 8(B)).
The count number decoder 7 resets the signals A, B and C in response to the counter-clearing signal CC ("0").
A flip-flop 5 masks signals (hereafter termed "the F/F for masking signals") from the trailing-edge detecting circuit 1 and the count number decoder 7. Specifically, flip-flop 5 sets an input-masking signal MI in response to the generation of the mask-canceling signal B, and resets the input-masking signal MI in response to supply of the trailing edge-detecting signal E.
After generation of SH, there is no masking signal generated so that an outside SY may be input to create noise. The conventional circuit takes the first trailing edge after the vertical synchronous period which may be an H or Q signal. Then, the detector detects Q for the H synchronizing signal until a pulse is lost and the circuit resynchronizes itself.
An AND gate 2 performs a logical-AND operation between the edge-detecting signal E and the input-masking signal MI. An OR gate 3 performs a logical-OR operation between the output of the AND gate 2 and the self-generated output signal C from the count number decoder 7.
A flip-flop 4 for H-signals (horizontal sync signals) (hereafter termed "the F/F for H-signals") sets the horizontal synchronizing output SH of the output in response to a high-level output through the OR gate 3, and resets the horizontal synchronizing output SH in response to the high level of the H-output reset signal A.
Below, the operation of the conventional horizontal synchronizing signal-generating circuit will be explained with reference to FIG. 7 and to FIGS. 8(A)-8(B) which is a time chart illustrating waveforms at individual sections of the conventional circuit.
The trailing-edge detecting circuit 1 generates an edge-detecting signal E upon detection of a trailing edge of the composite synchronizing signal SY.
With this edge-detecting signal E, the output through the AND gate 2 is switched to a high level "1" (assuming that the input-masking signal MI is at a high level "1"), and the counter-clearing signal CC outputted through the OR gate 3 is switched to a high level ("1") as well. The counter-clearing signal CC initializes the counter 6 to zero, and simultaneously sets the F/F for H-signals 4 to switch the horizontal synchronizing output SH to a high level.
Simultaneously (e.g., in parallel), the edge-detecting signal E resets the F/F for masking signals 5. Therefore, the input of the edge-detecting signal E is disabled from this time until generation of a mask-cancelling signal B. Additionally, the counter-clearing signal CC initializes the outputs A, B and C of the count number decoder 7 to respective low levels simultaneously with the initialization of the counter 6. It is noted that the FF 5 has a certain delay therein which allows MI to go high substantially instantaneously with the trailing edge detection signal.
The counter 6, after having been initialized by the counter-clearing signal CC, restarts counting-up upon input of a counter clock CK pulse from a clock (not illustrated). Then, the count number decoder 7 begins monitoring to detect whether the count number N of the counter 6 is equal to the first setting. When a match is detected (e.g., count number N of the counter 6 is equal to the first setting), the count number decoder 7 switches the H-output reset signal A to a high level.
In response to the H-output reset signal A, the F/F 4 for H-signals is reset, and the horizontal synchronizing output SH of the output is switched to a low level (e.g., "0"). As mentioned above, since the pulse width of the horizontal synchronizing inputs of the composite synchronizing signal SY is on the order of 5 .mu.s, the first setting is set to such a value that matching occurs 5 .mu.s after initialization of the counter 6.
When the above operation is completed, a first horizontal synchronizing input is extracted from the composite synchronizing signal SY.
When the counter 6 continues counting up, and the count number N matches the second setting, a mask-canceling signal B is generated, and the F/F 5 for masking signals sets an input-masking signal MI.
It is noted that the relationship between the counter 6 and the outputs A, B, and C is determined by whether they match or not. For example, when the output of the decoder "matches the second setting" "B" is output. Thus, the respective first, second and third settings of the clock counter (e.g., the first second or third clock counts) triggers outputs A, B, and C.
Here, the edge-detecting signal E outputted through the trailing-edge detecting circuit 1 is enabled. That is, as mentioned above, the second setting is the period during which the edge-detecting signal E is disabled, to prevent false inputting of the composite synchronizing signal SY due to noise, etc. As further mentioned above, the second setting is usually set to approximately 93-95% of the cycle of the horizontal synchronizing inputs (e.g., approximately 63.5 .mu.s), or 60 .mu.s in this case.
When the composite synchronizing signal SY has no loss of horizontal synchronizing input, the trailing-edge-detecting circuit 1 detects a trailing edge of the composite synchronizing signal SY and outputs a trailing-edge-detecting signal E before the count number N attains the third setting.
In response to the output of the edge-detecting signal E, the OR gate 3 sets a counter-clearing signal CC to initialize the counter 6 to zero. The initialization of the counter 6 results in resetting the respective output signals A-C of the count number decoder 7 as well. Subsequent operation is the same as described above, and thus reference thereto is omitted. The disablement period allows the horizontal synchronizing inputs to be identified immediately after the vertical synchronous period.
The composite synchronizing signal SY may lose some portions when the receiving state of the respective radio wave is temporarily impaired. To counter such a loss, self-generation of the horizontal synchronizing output SH may be performed, as discussed below and as shown in the waveform of FIGS. 8(A) and 8(b).
Specifically, since no edge-detecting signal E is generated even after the input-masking signal MI has been switched to a high level, the AND gate 2 remains at the low level, and no counter-clearing signal CC is generated. Therefore, the counter 6 continues the counting operation.
Then, when the count number of the counter 6 matches the third setting of the count number decoder 7, the self-generated output signal C is switched to a high level, and thus the output of the OR gate 3 is switched to a high level as well.
This results in almost the same state as when an edge-detecting signal E has been generated, and the counter-clearing signal CC initializes the counter 6 and the count number decoder 7, while the F/F 4 for H-signals switches the horizontal synchronizing output SH to a high level. The only difference between the above-described state and when an edge-detecting signal E is generated is that the F/F 5 for masking signals is not reset. Accordingly, trailing edges of the composite synchronizing signals SY inputted after this point in time are received without error.
Thus, when the composite synchronizing signal SY has some lost portions and self-generation of the horizontal synchronizing output SH is performed, the composite synchronizing signals SY inputted thereafter are not ignored and are received preferentially.
As described above, the conventional horizontal synchronizing signal-generating circuit, including the trailing-edge detector 1, detects trailing edges of composite synchronizing signals SY from an external source, and outputs horizontal synchronizing outputs SH. Further, after detection of the edges, the process enters input-masking terms to prevent malfunction due to noise, radio wave impairment, etc. Additionally, the circuit self-generates the horizontal synchronizing outputs SH in preparation for times when the composite synchronizing signals SY lose some portions thereof (or are completely lost).
However, when VTR sets are actually used (as well as broadcast TV signals), horizontal synchronizing signals, serrated pulses, equalizing pulses, etc. are sometimes not inputted during periods of vertical synchronizing signals. This is a problem.
Specifically, the waveform of inputted composite synchronizing signals becomes flat (e.g., even) due to great attenuation of the above pulse level during vertical synchronous periods, as shown in FIGS. 3(A) and 3(B), depending on the method of establishing a connection between the output device (not shown) for the composite synchronizing signals and the input terminal TI for the composite synchronizing signals.
For example, when the composite synchronizing signal-transmitting signal line is connected to a power supply via a pull-up resistor, the impedance at the output end changes at the low level as well as the high level, and since this results in a longer transition time from the low-level to the high-level than the transition time from the high-level to the low-level, the narrow pulses at the high-level become flat.
Further, due to the phase relationship between the vertical synchronous terms and the horizontal synchronizing inputs, the composite synchronizing signals are of two types, the odd field and the even field, as shown in FIG. 6.
The above considerations (e.g., the narrow pulses at the high-level becoming flat and the composite synchronizing signals being of the odd field-type and the even field-type) cause the following problems.
Namely, input of composite synchronizing signals of waveforms with loss of narrow pulses such as horizontal synchronizing signals and equalizing pulses during vertical synchronizing signal periods as described above, always results in output of horizontal synchronizing outputs SH by self-generation during the vertical synchronous periods, and thus in receipt of trailing-edges of later-inputted composite synchronizing signals SY as horizontal synchronizing inputs.
However, since the vertical synchronous terms and the horizontal synchronous inputs have two phase relationships, equalizing pulses are erroneously received as horizontal synchronous inputs only in the case of the odd field. The "even field" will not face such problems since the first pulse immediately after the vertical synchronous period is always the horizontal pulse for the "even field".
Since composite synchronizing signals of waveforms with lost narrow pulses, including horizontal synchronizing inputs, are inputted during vertical synchronous periods, self-generated horizontal synchronizing inputs are outputted during vertical synchronous periods without exception. Additionally, the trailing-edges of the later-inputted composite synchronizing signals are always recognized as the horizontal synchronous inputs to erroneously receive equalizing pulses as the horizontal synchronous inputs in the case of the odd field.
Referring to FIGS. 9(A) and 9(B), the relationship among the composite synchronizing signal SY with lost narrow pulses during the vertical synchronous periods, the input-masking signal MI and the horizontal synchronizing signal SH for each of the odd/even fields, and the operation for extracting the horizontal synchronizing inputs is shown for the odd field and the even field. As shown and as mentioned above, with the conventional circuit, horizontal synchronizing inputs may be extracted erroneously immediately after the vertical synchronous periods.
In view of the foregoing, the above conventional horizontal synchronizing signal-generating circuit cannot extract the horizontal synchronizing inputs immediately after the vertical synchronous periods, and the corresponding horizontal synchronizing outputs cannot be outputted. As a result, horizontal synchronization is not efficiently performed and indeed may be improperly performed.
Moreover, after generation of the SH signal, there is no masking signal MI generated so that an outside SY signal may be input to create noise.